Quote from: stride on November 15, 2016, 06:08:44 amAnyhow, I recently made a wirespeed Ethernet packet sniffer on my development board, all pure logic - no CPU, big fun. I want to extend on that.
That's very impressive. It must have been a steep learning curve if you came straight from software into an FPGA. Gigabit Ethernet is going to be a tough one for a first board but given what you've achieved already I'm sure you're up to figuring out the hard parts. Board layout will be crucial at the speeds involved here. If the manufacturer has a development board where you can see the PCB layout then use it as a reference.
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- Since I'm not using the internal LDO, can I drop connecting it?
The datasheet says that you can leave it floating in the pinout table. Question is, why not use it? An LDO is going to be quieter than a switcher and the LDO onboard is going to be matched to the requirements of the chip.
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- Do I still need capacitors close to the power pins on the PHY chip? (As in Figure 7 from the app notes)
Yes, and they'll need to be good quality which means X5R/X7R for the larger ceramics and C0G/NP0 for the smaller ones.
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- What is the recommended way to wire up the DVDDH 3.3V?
It looks like it sets the level for the digital IO interface. So supply it with 3.3/2.5/1.8V to match the IO levels coming from the FPGA board.