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When ever I set my RD, CS, WR, RS pins to their alternate function, my FMC stops streaming. Time to dig deeper  .

It might be timing. If you have a logic analyser then probe WR and some data lines to see how long your write transaction is versus the limits in the datasheet. The F429 is a very fast device and you could be exceeding the LCD timing limits when using the FMC. Setting the lines manually with GPIO will be much, much slower and could be bringing you back into spec.

Also, CS is usually not required and can be tied low (active).

$80 is a great price for a V3 board though. You can build a powerful workstation around that.

A workaround is now in place for the 5.4.1 regression so the latest release can now be used.

This is now fixed on the master branch. If you sync from github you should get the fix.

See issue:
https://github.com/andysworkshop/stm32plus/issues/193

I've now completed my build of a power supply controller around this module and the write up will appear in a blog article in about 2 weeks when I've had time to fully write it up. It's looking great and performing really well!

Video encoding is CPU intensive,

It certainly is. For fun I recently wrote a Premiere Pro VP9 exporter plugin that drives the libvpx encoder in a novel way so as to get 100% CPU usage out of it and it still takes much longer to export than H.264.

Hello guys!

I was was impressed with the capabilities of the HP Z800/820  in video production. At first, I was looking on ebay for a barebone Z820 to build up.  After some Googling I came across Andy's Z800 build blog, which is amazing. Now I'm leaning toward going this route--using a Z820 motherboard and 2x E6-2670.    I saw some ES version CPUs on ebay, should I stay away from them? TIA

I haven't heard any good reason to not use the engineering samples. As long as there are no critical bug fixes in the later steppings you should be fine.

I am monitoring the ebay prices of C612 chipset boards. They are still expensive and the Z820 board is not yet a bargain amongst them, plus you have to mod your case to fit it. If I were to buy right now then I'd probably get a Gigabyte MD70 or Asus Z10PE.

The E5 V3 CPUs are starting to fall in price and there's some great deals around from HK/Chinese sellers on the 12/14/16 core models. If the motherboards weren't holding their prices so well then I'd be sorely tempted myself.

Do You know is this GPSDO has a PLL or FLL control ?
one of classic problem with FLL is like BG7TL GPSDO is not "accurate" freq generated I believe come from rounding in digital counting thats why PLL more desirable but PLL has another problem about loop filter time constant if it use analog loop filter we deal with capacitor imperfection etc. if this Symetricom board has PLL and can control the time loop constant in digital to match the OCXO drift that will be wonderful.

The status command reports the PLL mode - you can see it in the main article. So it would appear that there is a PLL inside.

As long as the technical specs of the memory match those in the HP Z800 Memory Configuration and Optimization document then you should be fine. My own 48Gb is a mix of hynix and samsung modules from different sources and it works perfectly. Just make sure your configuration matches one of those in HP's document and be aware of the performance warning about using quad rank memory (the 800MHz limit)

The short answer is 'no' I'm afraid. Only the free 'GNU ARM Embedded Toolchain' maintained by engineers from ARM is supported.

It is quite a reliable technique. I find that I can go around a board with the iron in my right hand and the solder wire in my left and quickly dab over all pads down to 0603 size.

The TSOP, QFP and QFN ICs I do by loading up the iron with solder then dragging the molten blob across a row of pads leaving behind little bumps of solder on each. If I've got my flux right then this normally works fine. Sometimes though I have to go back and either undo a bridge or add more solder to a pad (usually the first one in a row). You don't need braid to undo a bridge. Normally if you smother the bridge in flux, clean your iron then just touch the bridge the solder will shrink back to the pads. Usually.

I'm designing using these assumptions:
- The capacitors can be fed from the power supply through any number of vias, the point is to have a steady trickle of power.
- The capacitors is the actual elements feeding the IC, they should have an as short path as possible between Vcc and GND on the IC.
- The big capacitor is the one feeding the smaller ones.

Are my assumptions correct?

Not quite correct I'm afraid.

The capacitors can be fed from the power supply through any number of vias, the point is to have a steady trickle of power.
Yes to the first part but the point is to have them charge up to capacity and then when they're depleted by a demand for power from the IC they can charge back to capacity fast.

- The capacitors is the actual elements feeding the IC, they should have an as short path as possible between Vcc and GND on the IC.
The IC is generally fed by its power pins. High speed switching inside the IC causes rapid demands for power that can cause dips in the supply voltage if the supply is distant from the IC. The capacitors are there to respond to those high frequency demands by acting as little reservoirs, if you like. That's why they are placed as close as possible to the IC. It's normal practice to place the smallest cap (highest frequency) nearest the IC and the largest (lowest frequency) furthest away. Yes you want a short path to ground from the cap. A via down to a ground plane is normal practice.

- The big capacitor is the one feeding the smaller ones.
It's likely that they will do that but their main purpose is to respond to lower frequency switching demands from the IC.

Always choose good quality brands and try to use technologies with low ESR.

In your schematic I would move the ceramics closer to the pin they're decoupling and each one should have its own via to ground. With this being a high speed design I would consider moving to 4 layers. Having an unbroken ground plane on the first inner layer is a big plus for signal integrity especially if there are any differential pairs on the board. And then being able to devote the second inner layer to just your power rails means that you can just put down vias wherever you need to feed something with power.

I'm designing using these assumptions:
- The capacitors can be fed from the power supply through any number of vias, the point is to have a steady trickle of power.
- The capacitors is the actual elements feeding the IC, they should have an as short path as possible between Vcc and GND on the IC.
- The big capacitor is the one feeding the smaller ones.

Are my assumptions correct?

Not quite correct I'm afraid.

The capacitors can be fed from the power supply through any number of vias, the point is to have a steady trickle of power.
Yes to the first part but the point is to have them charge up to capacity and then when they're depleted by a demand for power from the IC they can charge back to capacity fast.

- The capacitors is the actual elements feeding the IC, they should have an as short path as possible between Vcc and GND on the IC.
The IC is generally fed by its power pins. High speed switching inside the IC causes rapid demands for power that can cause dips in the supply voltage if the supply is distant from the IC. The capacitors are there to respond to those high frequency demands by acting as little reservoirs, if you like. That's why they are placed as close as possible to the IC. It's normal practice to place the smallest cap (highest frequency) nearest the IC and the largest (lowest frequency) furthest away. Yes you want a short path to ground from the cap. A via down to a ground plane is normal practice.

- The big capacitor is the one feeding the smaller ones.
It's likely that they will do that but their main purpose is to respond to lower frequency switching demands from the IC.

Always choose good quality brands and try to use technologies with low ESR.

When I install the H310, though, I get a series of boot errors from the BIOS about Slots 1 & 2 on both CPUs:

207--Incompatible DIMMs detected
203--Memory module failed self-test and failing rank was disabled
204--Memory module failed and user rank was disabled

I'm assuming that you've disabled the onboard SAS controller and it made no difference. If you don't need to boot from this card, can you try going into the BIOS 'Advanced' menu and select the PCIe slot containing your card. There will be an option 'Download option ROM'. Try disabling it.

I also assume that the Dell card has its own BIOS that you can get into during bootup. Look for anything in there related to how it interacts with the computer BIOS during the boot phase that you can change. This option ROM setup will not be visible if you've disabled 'download option ROM' as my first suggestion.

I decided to make one of these I presume as you put the board schematics up it's ok with you to simply send the design to seeed or whoever to get some boards made?

Absolutely yes, that's what I hope people will do.

I have a project in mind that I'd making my own board (very slowly designing it) but figured that making of of these would 1) Test my construction skills on a similar sized project and 2) actually be something where I'd make use of the finished product.

(Just thought you'd like to know there is interest in your work so you might be encouraged to keep posting things like this!)

Thanks very much, I'll definitely keep posting as the ideas keep flowing.