Author Topic: GPIO Daughter Board Design  (Read 4389 times)

stride

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GPIO Daughter Board Design
« on: November 15, 2016, 06:08:44 am »
Hello guys,

I'm a hobbyist mostly into software engineering, in addition into doing stuff on my DE2-115 Cyclone IV FPGA development board.
Unfortunately I have only rudimentary skills on electronics and analogous systems...

Anyhow, I recently made a wirespeed Ethernet packet sniffer on my development board, all pure logic - no CPU, big fun. I want to extend on that.

To learn a bit in the electronics area my goal now is to make a GPIO connected Daughter Board for the dev-kit, with a couple of Ethernet PHY's on it.


I've collected some information and installed TinyCAD for initial schematics.

GPIO header details from the DE2 manual: https://1drv.ms/i/s!AgV35ZnXdrAGghgrNiEJro6ZHbDj

The PHY chip I want to use: http://ww1.microchip.com/downloads/en/DeviceDoc/00002117C.pdf

Some manufacturer notes regarding power: http://ww1.microchip.com/downloads/en/AppNotes/ANLAN206.pdf
(I've opted for a solution as in Figure 11)

And finally, my initial schematics for power rails!  :) https://1drv.ms/i/s!AgV35ZnXdrAGghck96jI1YGuXq2z
(Please forgive my newbie mistakes)

I have a couple of questions that I would really appreciate help with:
 - Since I'm not using the internal LDO, can I drop connecting it?
 - Do I still need capacitors close to the power pins on the PHY chip? (As in Figure 7 from the app notes)
 - What is the recommended way to wire up the DVDDH 3.3V?


With best Regards,

/stride
« Last Edit: November 15, 2016, 06:11:25 am by stride »

Andy Brown

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Re: GPIO Daughter Board Design
« Reply #1 on: November 15, 2016, 02:51:47 pm »
Anyhow, I recently made a wirespeed Ethernet packet sniffer on my development board, all pure logic - no CPU, big fun. I want to extend on that.
That's very impressive. It must have been a steep learning curve if you came straight from software into an FPGA. Gigabit Ethernet is going to be a tough one for a first board but given what you've achieved already I'm sure you're up to figuring out the hard parts. Board layout will be crucial at the speeds involved here. If the manufacturer has a development board where you can see the PCB layout then use it as a reference.

Quote
- Since I'm not using the internal LDO, can I drop connecting it?
The datasheet says that you can leave it floating in the pinout table. Question is, why not use it? An LDO is going to be quieter than a switcher and the LDO onboard is going to be matched to the requirements of the chip.

Quote
- Do I still need capacitors close to the power pins on the PHY chip? (As in Figure 7 from the app notes)
Yes, and they'll need to be good quality which means X5R/X7R for the larger ceramics and C0G/NP0 for the smaller ones.

Quote
- What is the recommended way to wire up the DVDDH 3.3V?
It looks like it sets the level for the digital IO interface. So supply it with 3.3/2.5/1.8V to match the IO levels coming from the FPGA board.
It's worse than that, it's physics Jim!

stride

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Re: GPIO Daughter Board Design
« Reply #2 on: November 16, 2016, 06:12:24 am »
Making the sniffer? Not that hard really.

I found it practical to start out with the smallest VHDL entities while learning the language and typical approaches.
Deciding on the requirements and having test-bench simulations for each and every one was crucial...

Moving from a sequential algorithm mindset into custom parallel circuits and the power of a single clock cycle was almost a religious experience :)
After that it was just a matter of combining the entities to provide the larger solution.
Surprisingly simple actually, a state machine for MDIO control, dual clock FIFO for receiving the 125 MHz DDR nibbles using the source clock from the PHY. Once received into the FIFO use an internal clock to pull data out and a shift-register/pipeline approach to decode and act apprpriately on the ethernet frames. It could make an amazing firewall...


Very impressed by the work you did on that CPU, FPGA, Sprite and framebuffer thing btw, seeing it got me into trying to do hardware.


Anyhow, my attention is now on power-rails, and I did find this excellent writeup: http://www.interfacebus.com/Design_Capacitors.html

And ofc the evaluation board details for the PHY! http://www.microchip.com/DevelopmentTools/ProductDetails.aspx?PartNO=ksz9031rnx-eval


Wish me luck, and forgive stupid questions? Hahahaa...

/stride
« Last Edit: November 16, 2016, 06:15:40 am by stride »

stride

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Re: GPIO Daughter Board Design
« Reply #3 on: November 19, 2016, 05:40:42 am »
Guys... a quick sanity check to see if I got this decoupling concept right?

In my case there are several "power-rails", each of them typically terminates on 3 pins on the IC.
 - IC is a QFN package with a GND pad underneath.
 - The "power feed" consists of 4 capacitors, a TANT + 3 ceramic.

I'm designing using these assumptions:
 - The capacitors can be fed from the power supply through any number of vias, the point is to have a steady trickle of power.
 - The capacitors is the actual elements feeding the IC, they should have an as short path as possible between Vcc and GND on the IC.
 - The big capacitor is the one feeding the smaller ones.

Are my assumptions correct?

Have a look at the attached image, it's my first PCB design attempt - doing the power rails first :)
All and any feedback welcome!


/stride

Andy Brown

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Re: GPIO Daughter Board Design
« Reply #4 on: November 19, 2016, 09:10:41 am »
I'm designing using these assumptions:
 - The capacitors can be fed from the power supply through any number of vias, the point is to have a steady trickle of power.
 - The capacitors is the actual elements feeding the IC, they should have an as short path as possible between Vcc and GND on the IC.
 - The big capacitor is the one feeding the smaller ones.

Are my assumptions correct?
Not quite correct I'm afraid.

The capacitors can be fed from the power supply through any number of vias, the point is to have a steady trickle of power.
Yes to the first part but the point is to have them charge up to capacity and then when they're depleted by a demand for power from the IC they can charge back to capacity fast.

- The capacitors is the actual elements feeding the IC, they should have an as short path as possible between Vcc and GND on the IC.
The IC is generally fed by its power pins. High speed switching inside the IC causes rapid demands for power that can cause dips in the supply voltage if the supply is distant from the IC. The capacitors are there to respond to those high frequency demands by acting as little reservoirs, if you like. That's why they are placed as close as possible to the IC. It's normal practice to place the smallest cap (highest frequency) nearest the IC and the largest (lowest frequency) furthest away. Yes you want a short path to ground from the cap. A via down to a ground plane is normal practice.

- The big capacitor is the one feeding the smaller ones.
It's likely that they will do that but their main purpose is to respond to lower frequency switching demands from the IC.

Always choose good quality brands and try to use technologies with low ESR.
It's worse than that, it's physics Jim!

Andy Brown

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Re: GPIO Daughter Board Design
« Reply #5 on: November 19, 2016, 09:16:02 am »
I'm designing using these assumptions:
 - The capacitors can be fed from the power supply through any number of vias, the point is to have a steady trickle of power.
 - The capacitors is the actual elements feeding the IC, they should have an as short path as possible between Vcc and GND on the IC.
 - The big capacitor is the one feeding the smaller ones.

Are my assumptions correct?
Not quite correct I'm afraid.

The capacitors can be fed from the power supply through any number of vias, the point is to have a steady trickle of power.
Yes to the first part but the point is to have them charge up to capacity and then when they're depleted by a demand for power from the IC they can charge back to capacity fast.

- The capacitors is the actual elements feeding the IC, they should have an as short path as possible between Vcc and GND on the IC.
The IC is generally fed by its power pins. High speed switching inside the IC causes rapid demands for power that can cause dips in the supply voltage if the supply is distant from the IC. The capacitors are there to respond to those high frequency demands by acting as little reservoirs, if you like. That's why they are placed as close as possible to the IC. It's normal practice to place the smallest cap (highest frequency) nearest the IC and the largest (lowest frequency) furthest away. Yes you want a short path to ground from the cap. A via down to a ground plane is normal practice.

- The big capacitor is the one feeding the smaller ones.
It's likely that they will do that but their main purpose is to respond to lower frequency switching demands from the IC.

Always choose good quality brands and try to use technologies with low ESR.

In your schematic I would move the ceramics closer to the pin they're decoupling and each one should have its own via to ground. With this being a high speed design I would consider moving to 4 layers. Having an unbroken ground plane on the first inner layer is a big plus for signal integrity especially if there are any differential pairs on the board. And then being able to devote the second inner layer to just your power rails means that you can just put down vias wherever you need to feed something with power.
It's worse than that, it's physics Jim!

stride

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Re: GPIO Daughter Board Design
« Reply #6 on: November 20, 2016, 08:37:21 am »
Thanks mate for your opinions! :)

I've reworked it somehow; a ground plane and another for the power-rails.
This time focusing on the 1.2 V AVDLL_PLL power needed, I'm letting it enter a "power island" before going into the terminating caps and the pin on the chip.

Component U3 is bringing down the power from 3.3 to 1.2, according to the data-sheet it requires a cap pretty close on the Vout pin.

Have a look at my attachment and voice your opinion guys! I've included the schematics and the pcb implementation.
Help is very much appreciated while I'm learning these things :)


/stride