• Welcome to Andy's Workshop Forums. Please login or sign up.
 
March 28, 2024, 10:57:35 pm

News:

SMF - Just Installed!


Show posts

This section allows you to view all posts made by this member. Note that you can only see posts made in areas you currently have access to.

Messages - stride

1
Hello :)

Pico-ITX? For simplicity put any standard OS to interface with your peripherals, perhaps even a touch screen?
You would have to make a gauge/dash program tho.

http://www.viatech.com/en/boards/pico-itx/

But hey... you could have your mp3 and movie library, a nav program and lots of other stuff there too :)

Or perhaps a RaspBerry? http://engineering-diy.blogspot.fr/2015/01/raspberry-pi-carpc-january-2015-updates.html
If your hardware and programming skills are limited xbmc/kodi even runs on Windows! You'll probably just need to find the right plugins.



/stride
2
Hardware projects / Re: GPIO Daughter Board Design
November 20, 2016, 08:37:21 am
Thanks mate for your opinions! :)

I've reworked it somehow; a ground plane and another for the power-rails.
This time focusing on the 1.2 V AVDLL_PLL power needed, I'm letting it enter a "power island" before going into the terminating caps and the pin on the chip.

Component U3 is bringing down the power from 3.3 to 1.2, according to the data-sheet it requires a cap pretty close on the Vout pin.

Have a look at my attachment and voice your opinion guys! I've included the schematics and the pcb implementation.
Help is very much appreciated while I'm learning these things :)


/stride
3
Hardware projects / Re: GPIO Daughter Board Design
November 19, 2016, 05:40:42 am
Guys... a quick sanity check to see if I got this decoupling concept right?

In my case there are several "power-rails", each of them typically terminates on 3 pins on the IC.
- IC is a QFN package with a GND pad underneath.
- The "power feed" consists of 4 capacitors, a TANT + 3 ceramic.

I'm designing using these assumptions:
- The capacitors can be fed from the power supply through any number of vias, the point is to have a steady trickle of power.
- The capacitors is the actual elements feeding the IC, they should have an as short path as possible between Vcc and GND on the IC.
- The big capacitor is the one feeding the smaller ones.

Are my assumptions correct?

Have a look at the attached image, it's my first PCB design attempt - doing the power rails first :)
All and any feedback welcome!


/stride
4
Hardware projects / Re: GPIO Daughter Board Design
November 16, 2016, 06:12:24 am
Making the sniffer? Not that hard really.

I found it practical to start out with the smallest VHDL entities while learning the language and typical approaches.
Deciding on the requirements and having test-bench simulations for each and every one was crucial...

Moving from a sequential algorithm mindset into custom parallel circuits and the power of a single clock cycle was almost a religious experience :)
After that it was just a matter of combining the entities to provide the larger solution.
Surprisingly simple actually, a state machine for MDIO control, dual clock FIFO for receiving the 125 MHz DDR nibbles using the source clock from the PHY. Once received into the FIFO use an internal clock to pull data out and a shift-register/pipeline approach to decode and act apprpriately on the ethernet frames. It could make an amazing firewall...


Very impressed by the work you did on that CPU, FPGA, Sprite and framebuffer thing btw, seeing it got me into trying to do hardware.


Anyhow, my attention is now on power-rails, and I did find this excellent writeup: http://www.interfacebus.com/Design_Capacitors.html

And ofc the evaluation board details for the PHY! http://www.microchip.com/DevelopmentTools/ProductDetails.aspx?PartNO=ksz9031rnx-eval


Wish me luck, and forgive stupid questions? Hahahaa...

/stride
5
Hardware projects / GPIO Daughter Board Design
November 15, 2016, 06:08:44 am
Hello guys,

I'm a hobbyist mostly into software engineering, in addition into doing stuff on my DE2-115 Cyclone IV FPGA development board.
Unfortunately I have only rudimentary skills on electronics and analogous systems...

Anyhow, I recently made a wirespeed Ethernet packet sniffer on my development board, all pure logic - no CPU, big fun. I want to extend on that.

To learn a bit in the electronics area my goal now is to make a GPIO connected Daughter Board for the dev-kit, with a couple of Ethernet PHY's on it.


I've collected some information and installed TinyCAD for initial schematics.

GPIO header details from the DE2 manual: https://1drv.ms/i/s!AgV35ZnXdrAGghgrNiEJro6ZHbDj

The PHY chip I want to use: http://ww1.microchip.com/downloads/en/DeviceDoc/00002117C.pdf

Some manufacturer notes regarding power: http://ww1.microchip.com/downloads/en/AppNotes/ANLAN206.pdf
(I've opted for a solution as in Figure 11)

And finally, my initial schematics for power rails!  :) https://1drv.ms/i/s!AgV35ZnXdrAGghck96jI1YGuXq2z
(Please forgive my newbie mistakes)

I have a couple of questions that I would really appreciate help with:
- Since I'm not using the internal LDO, can I drop connecting it?
- Do I still need capacitors close to the power pins on the PHY chip? (As in Figure 7 from the app notes)
- What is the recommended way to wire up the DVDDH 3.3V?


With best Regards,

/stride