What is needed to effectively use the Tearing Effect signaling? I have the demo working for the Vivaz U5 LCD and am trying to get rid of the tearing effects when drawing. From what I can glean from your site, I just need to connect the TE pin of the LCD to a free pin on the STM32, and then wait for it to trigger to draw to the screen. I've tried something like this:
GpioB<DefaultDigitalInputFeature<0> > pb;
_gl->enableTearingEffect(_gl->TE_VBLANK_HBLANK);
With the TE signal routed to PB0 of the F4 Discovery board I'm using. I can see that pin toggling on a scope so I know the output is working. Then in the code before drawing I have:
while(pb[0].read());
//drawing code (lines, rectangles, etc.)
Yet I still see tearing as if I didn't bother with the TE signal at all. I've tried various combinations (like using TE_VBLANK only, using while(!pb[0].read())) and none are better than doing nothing at all. I'm guessing I'm just not doing it properly. Could you point me in the right direction? Thanks!
The TE signal triggers at the beginning of the vertical blanking period and should be used as a trigger to redraw the display free from the possibility of crossing the refresh signal and causing the 'tearing effect' where the previous frame's data overlaps with the next frame's data. To do this successfully there are two conditions:
- You must complete your redraw faster than the refresh time (usually about 62Hz).
- You must redraw in the same direction as the refresh. That is, if the refresh runs from top left to bottom right then you must redraw in that direction too. Note that on the Vivaz U5 display the refresh always runs in 'portrait' mode even when you set the logical orientation to 'landscape'.
In practice that means that you can only really write out complete frames of data. If you try to issue commands that move the drawing window around the screen and then draw geometric figures then it's very likely that the refresh will catch up with you and you'll get tearing. Full-frame redraw with TE synchronisation is what I do in the FPGA graphics accelerator project and it frees up the MCU on that board to perform logic operations while the FPGA is pushing out data at full speed to the display.